Processor System Modelling

  ☕ A RISC-V microprocessor soft core Instruction Set Simulator (ISS), with source code

  ☕ A LatticeMico32 microprocessor soft core Instruction Set Simulator (ISS), with source code and embedded Linux case study

  ☕ A v8 SPARC RISC processor Instruction Set Simulator (ISS), with source code

  ☕ An 8051 microcontroller Instruction Set Simulator (ISS), with source code

  ☕ A 6502 8 bit microprocessor Instruction Set Simulator (ISS), with source code and a system model integration case study

HDL Design, Verification and Hardware System Modelling

  ☕  A RISC-V RV32I softcore CPU design in Verilog, targetting the terasIC Cyclone V FPGA (Intel) based DE10-Nano Development Board

  ☕  Article on a Virtual Processor (VProc) C/verilog high-speed simulation co-processing element

  ☕  A PCIe Virtual Host model traffic generator test component for Verilog. PCIe 1.1/2.0 up to 16 lanes—C API interface.

  ☕  A TCP/IPv4 packet generator, generating 10GbE packets over an XGMII interface

Digital Signal Processing

  ☕  Article on a Windows based Finite Impulse Response (FIR) filter design program, with source code

  ☕  Articles on LZ based lossless compression, with downloadable C, C++ and JAVA models

Graphics

  ☕  Articles on JPEG/JFIF concepts and format, reference C/C++ implementation and Verilog HDL decoder development

  ☕  Downloadable JPEG/JFIF decoding software source code

  🚧  Downloadable JPEG/JFIF Verilog HDL decoder package (currently under verification—no warranties whatsoever). See the Project Status section of the implementation documentation for current state)

  ☕  Downloadable bitmap image manipulation command line utility, bmp